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Merge branch 'develop' of github.com:ThundeRatz/STM32RF24
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@pedroazeredo04
pedroazeredo04 committed Aug 7, 2023
2 parents c22bd80 + 3b3a60e commit f2b4001
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Showing 3 changed files with 84 additions and 42 deletions.
94 changes: 56 additions & 38 deletions src/rf24.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ rf24_status_t rf24_init(rf24_dev_t* p_dev) {

if (dev_status == RF24_SUCCESS) {
reg_config.prim_rx = 0;
rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}
}
Expand Down Expand Up @@ -215,9 +215,11 @@ rf24_status_t rf24_power_up(rf24_dev_t* p_dev) {
}
}

reg_config.pwr_up = 1;
rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
reg_config.pwr_up = 1;
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}

rf24_delay(5);

Expand All @@ -238,10 +240,12 @@ rf24_status_t rf24_power_down(rf24_dev_t* p_dev) {
}
}

rf24_platform_disable(&(p_dev->platform_setup));
reg_config.pwr_up = 0;
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
rf24_platform_disable(&(p_dev->platform_setup));
reg_config.pwr_up = 0;
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}

return dev_status;
}
Expand Down Expand Up @@ -405,12 +409,16 @@ rf24_status_t rf24_open_writing_pipe(rf24_dev_t* p_dev, uint8_t* address) {
p_dev->addr_width);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

platform_status = rf24_platform_write_register(&(p_dev->platform_setup), NRF24L01_REG_TX_ADDR, address,
p_dev->addr_width);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_write_register(&(p_dev->platform_setup), NRF24L01_REG_TX_ADDR, address,
p_dev->addr_width);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}

platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_RX_PW_P0, p_dev->payload_size);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_RX_PW_P0, p_dev->payload_size);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}

return dev_status;
}
Expand All @@ -437,9 +445,11 @@ rf24_status_t rf24_open_reading_pipe(rf24_dev_t* p_dev, uint8_t pipe_number, uin

dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), m_child_payload_size[pipe_number],
p_dev->payload_size);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), m_child_payload_size[pipe_number],
p_dev->payload_size);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}
} else {
dev_status = RF24_INVALID_PARAMETERS;
}
Expand Down Expand Up @@ -505,8 +515,10 @@ rf24_status_t rf24_start_listening(rf24_dev_t* p_dev) {
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_CONFIG, reg_config.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, reg_status.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, reg_status.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}
}
}

Expand Down Expand Up @@ -610,8 +622,10 @@ rf24_status_t rf24_available(rf24_dev_t* p_dev, uint8_t* pipe_number) {
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}

if (reg_fifo_status.rx_empty) {
dev_status = RF24_RX_FIFO_EMPTY;
if (dev_status == RF24_SUCCESS) {
if (reg_fifo_status.rx_empty) {
dev_status = RF24_RX_FIFO_EMPTY;
}
}

if (dev_status == RF24_SUCCESS) {
Expand All @@ -634,10 +648,8 @@ rf24_status_t rf24_read(rf24_dev_t* p_dev, uint8_t* buff, uint8_t len) {

nrf24l01_reg_status_t status_reg = rf24_get_status(p_dev);

if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_read_payload(&(p_dev->platform_setup), buff, len);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}
platform_status = rf24_platform_read_payload(&(p_dev->platform_setup), buff, len);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

// Clears data ready interruption bit. But data ready utility still not implemented.
if (dev_status == RF24_SUCCESS) {
Expand All @@ -659,10 +671,8 @@ rf24_status_t rf24_write(rf24_dev_t* p_dev, uint8_t* buff, uint8_t len, bool ena
return RF24_TX_FIFO_FULL;
}

if (dev_status == RF24_SUCCESS) {
platform_status = rf24_platform_write_payload(&(p_dev->platform_setup), buff, len, enable_auto_ack);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);
}
platform_status = rf24_platform_write_payload(&(p_dev->platform_setup), buff, len, enable_auto_ack);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

if (dev_status == RF24_SUCCESS) {
rf24_platform_enable(&(p_dev->platform_setup));
Expand All @@ -676,20 +686,28 @@ rf24_status_t rf24_write(rf24_dev_t* p_dev, uint8_t* buff, uint8_t len, bool ena
rf24_platform_disable(&(p_dev->platform_setup));
}

// Max retries exceeded
if (status_reg.max_rt) {
dev_status = RF24_MAX_RETRANSMIT;
if (dev_status == RF24_SUCCESS) {
// Max retries exceeded
if (status_reg.max_rt) {
dev_status = RF24_MAX_RETRANSMIT;

status_reg.max_rt = 1; // Datasheet says to write 1 to clear the interruption bit.
rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, status_reg.value);
rf24_flush_tx(p_dev); // Only going to be 1 packet in the FIFO at a time using this method, so just flush.
status_reg.max_rt = 1; // Datasheet says to write 1 to clear the interruption bit.
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, status_reg.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_ERROR_CONTROL_INTERFACE);

return dev_status;
if (dev_status == RF24_SUCCESS) {
dev_status = rf24_flush_tx(p_dev); // Only going to be 1 packet in the FIFO at a time using this method, so just flush.
}

return dev_status;
}
}

status_reg.tx_ds = 1;
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, status_reg.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_INTERRUPT_NOT_CLEARED);
if (dev_status == RF24_SUCCESS) {
status_reg.tx_ds = 1;
platform_status = rf24_platform_write_reg8(&(p_dev->platform_setup), NRF24L01_REG_STATUS, status_reg.value);
dev_status = (platform_status == RF24_PLATFORM_SUCCESS) ? (RF24_SUCCESS) : (RF24_INTERRUPT_NOT_CLEARED);
}

return dev_status;
}
Expand Down
24 changes: 24 additions & 0 deletions src/rf24_debug.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_CONFIG */

nrf24l01_reg_config_t reg_config = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_CONFIG)};
(void) reg_config;
PRINTF(
"[00] CONFIG = 0x%02X | MASK_RX_DR=%d MASK_TX_DS=%d MASK_MAX_RT=%d EN_CRC=%d CRCO=%d PWR_UP=%d PRIM_RX=%d\r\n",
reg_config.value, reg_config.mask_rx_dr, reg_config.mask_tx_ds, reg_config.mask_max_rt,
Expand All @@ -65,6 +66,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_EN_AA */

nrf24l01_reg_en_aa_t reg_en_aa = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_EN_AA)};
(void) reg_en_aa;
PRINTF(
"[01] EN_AA = 0x%02X | ENAA_P5=%d ENAA_P4=%d ENAA_P3=%d ENAA_P2=%d ENAA_P1=%d ENAA_P0=%d\r\n",
reg_en_aa.value, reg_en_aa.enaa_p5, reg_en_aa.enaa_p4, reg_en_aa.enaa_p3,
Expand All @@ -76,6 +78,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_EN_RXADDR */

nrf24l01_reg_en_rxaddr_t reg_en_rxaddr = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_EN_RXADDR)};
(void) reg_en_rxaddr;
PRINTF(
"[02] EN_RXADDR = 0x%02X | ERX_P5=%d ERX_P4=%d ERX_P3=%d ERX_P2=%d ERX_P1=%d ERX_P0=%d\r\n",
reg_en_rxaddr.value, reg_en_rxaddr.erx_p5, reg_en_rxaddr.erx_p4, reg_en_rxaddr.erx_p3,
Expand All @@ -87,6 +90,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_SETUP_AW */

nrf24l01_reg_setup_aw_t reg_setup_aw = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_SETUP_AW)};
(void) reg_setup_aw;
PRINTF(
"[03] SETUP_AW = 0x%02X | AW=%d (%s)\r\n", reg_setup_aw.value, reg_setup_aw.aw,
(reg_setup_aw.aw == 0b00) ? "Illegal" : (reg_setup_aw.aw == 0b01) ? "3 bytes" : (reg_setup_aw.aw == 0b10) ? "4 bytes" : (reg_setup_aw.aw == 0b11) ? "5 bytes" : "???????"
Expand All @@ -97,6 +101,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_SETUP_RETR */

nrf24l01_reg_setup_retr_t reg_setup_retr = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_SETUP_RETR)};
(void) reg_setup_retr;
PRINTF(
"[04] SETUP_RETR = 0x%02X | ARD=%d (%d us) ARC=%d (retransmits)\r\n", reg_setup_retr.value,
reg_setup_retr.ard, 250 * (1 + reg_setup_retr.ard), reg_setup_retr.arc
Expand All @@ -107,6 +112,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_RF_CH */

nrf24l01_reg_rf_ch_t reg_rf_ch = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RF_CH)};
(void) reg_rf_ch;
PRINTF(
"[05] RF_CH = 0x%02X | RF_CH=%d (%d MHz)\r\n", reg_rf_ch.value,
reg_rf_ch.rf_ch, reg_rf_ch.rf_ch + 2400
Expand All @@ -117,6 +123,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_RF_SETUP */

nrf24l01_reg_rf_setup_t reg_rf_setup = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RF_SETUP)};
(void) reg_rf_setup;
PRINTF(
"[06] RF_SETUP = 0x%02X | CONT_WAVE=%d RF_DR=%d%d (%s) PLL_LOCK=%d RF_PWR=%d (%sdBm)\r\n",
reg_rf_setup.value, reg_rf_setup.cont_wave, reg_rf_setup.rf_dr_low, reg_rf_setup.rf_dr_high,
Expand All @@ -130,6 +137,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_STATUS */

nrf24l01_reg_status_t reg_status = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_STATUS)};
(void) reg_status;
PRINTF(
"[07] STATUS = 0x%02X | RX_DR=%d TX_DS=%d MAX_RT=%d RX_P_NO=%d TX_FULL=%d\r\n",
reg_status.value, reg_status.rx_dr, reg_status.tx_ds,
Expand All @@ -141,6 +149,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_OBSERVE_TX */

nrf24l01_reg_observe_tx_t reg_observe_tx = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_OBSERVE_TX)};
(void) reg_observe_tx;
PRINTF(
"[08] OBSERVE_TX = 0x%02X | PLOS_CNT=%d ARC_CNT=%d\r\n", reg_observe_tx.value,
reg_observe_tx.plos_cnt, reg_observe_tx.arc_cnt
Expand All @@ -151,6 +160,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_RPD */

nrf24l01_reg_rpd_t reg_rpd = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RPD)};
(void) reg_rpd;
PRINTF("[09] RPD = 0x%02X | RPD=%d\r\n", reg_rpd.value, reg_rpd.rpd);

rf24_delay(RF24_DEBUG_DELAY_MS); // Delay is needed so RTT can print the registers values.
Expand Down Expand Up @@ -180,12 +190,16 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_RX_ADDR_P2 to NRF24L01_REG_RX_ADDR_P5 */

nrf24l01_reg_1byte_addr_t reg_rx_addr_p2 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_ADDR_P2)};
(void) reg_rx_addr_p2;
PRINTF("[0C] RX_ADDR_P2 = 0x%02X\r\n", reg_rx_addr_p2.value);
nrf24l01_reg_1byte_addr_t reg_rx_addr_p3 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_ADDR_P3)};
(void) reg_rx_addr_p3;
PRINTF("[0D] RX_ADDR_P3 = 0x%02X\r\n", reg_rx_addr_p3.value);
nrf24l01_reg_1byte_addr_t reg_rx_addr_p4 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_ADDR_P4)};
(void) reg_rx_addr_p4;
PRINTF("[0E] RX_ADDR_P4 = 0x%02X\r\n", reg_rx_addr_p4.value);
nrf24l01_reg_1byte_addr_t reg_rx_addr_p5 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_ADDR_P5)};
(void) reg_rx_addr_p5;
PRINTF("[0F] RX_ADDR_P5 = 0x%02X\r\n", reg_rx_addr_p5.value);

rf24_delay(RF24_DEBUG_DELAY_MS); // Delay is needed so RTT can print the registers values.
Expand All @@ -204,23 +218,30 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_RX_PW_Px */

nrf24l01_reg_rx_pw_p0_t reg_rx_pw_p0 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P0)};
(void) reg_rx_pw_p0;
PRINTF("[11] RX_PW_P0 = 0x%02X\r\n", reg_rx_pw_p0.value);
nrf24l01_reg_rx_pw_p1_t reg_rx_pw_p1 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P1)};
(void) reg_rx_pw_p1;
PRINTF("[12] RX_PW_P1 = 0x%02X\r\n", reg_rx_pw_p1.value);
nrf24l01_reg_rx_pw_p2_t reg_rx_pw_p2 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P2)};
(void) reg_rx_pw_p2;
PRINTF("[13] RX_PW_P2 = 0x%02X\r\n", reg_rx_pw_p2.value);
nrf24l01_reg_rx_pw_p3_t reg_rx_pw_p3 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P3)};
(void) reg_rx_pw_p3;
PRINTF("[14] RX_PW_P3 = 0x%02X\r\n", reg_rx_pw_p3.value);
nrf24l01_reg_rx_pw_p4_t reg_rx_pw_p4 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P4)};
(void) reg_rx_pw_p4;
PRINTF("[15] RX_PW_P4 = 0x%02X\r\n", reg_rx_pw_p4.value);
nrf24l01_reg_rx_pw_p5_t reg_rx_pw_p5 = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_RX_PW_P5)};
(void) reg_rx_pw_p5;
PRINTF("[16] RX_PW_P5 = 0x%02X\r\n", reg_rx_pw_p5.value);

rf24_delay(RF24_DEBUG_DELAY_MS); // Delay is needed so RTT can print the registers values.

/* NRF24L01_REG_FIFO_STATUS */

nrf24l01_reg_fifo_status_t reg_fifo_status = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_FIFO_STATUS)};
(void) reg_fifo_status;
PRINTF(
"[17] FIFO_STATUS = 0x%02X | TX_REUSE=%d TX_FULL=%d TX_EMPTY=%d RX_FULL=%d RX_EMPTY=%d\r\n", reg_fifo_status.value,
reg_fifo_status.tx_reuse, reg_fifo_status.tx_full, reg_fifo_status.tx_empty, reg_fifo_status.rx_full, reg_fifo_status.rx_empty
Expand All @@ -231,6 +252,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_DYNPD */

nrf24l01_reg_dynpd_t reg_dynpd = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_DYNPD)};
(void) reg_dynpd;
PRINTF(
"[1C] DYNPD = 0x%02X | DPL_P5=%d DPL_P4=%d DPL_P3=%d DPL_P2=%d DPL_P1=%d DPL_P0=%d\r\n", reg_dynpd.value,
reg_dynpd.dpl_p5, reg_dynpd.dpl_p4, reg_dynpd.dpl_p3, reg_dynpd.dpl_p2,
Expand All @@ -242,6 +264,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {
/* NRF24L01_REG_FEATURE */

nrf24l01_reg_feature_t reg_feature = {rf24_debug_read_reg8(p_dev, NRF24L01_REG_FEATURE)};
(void) reg_feature;
PRINTF(
"[1D] FEATURE = 0x%02X | EN_DPL=%d EN_ACK_PAY=%d EN_DYN_ACK=%d\r\n", reg_feature.value,
reg_feature.en_dpl, reg_feature.en_ack_pay, reg_feature.en_dyn_ack
Expand All @@ -252,6 +275,7 @@ void rf24_debug_dump_registers(rf24_dev_t* p_dev) {

void rf24_debug_print_status(rf24_dev_t* p_dev) {
nrf24l01_reg_status_t reg_status = rf24_get_status(p_dev);
(void) reg_status;

PRINTF(
"[07] STATUS = 0x%02X | RX_DR=%d TX_DS=%d MAX_RT=%d RX_P_NO=%d TX_FULL=%d\r\n",
Expand Down
8 changes: 4 additions & 4 deletions src/rf24_platform.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ rf24_platform_status_t rf24_platform_read_register(rf24_platform_t* p_setup, nrf
hal_status = HAL_SPI_TransmitReceive(p_setup->hspi, &command, &(status_reg.value), 1, p_setup->spi_timeout);

if (hal_status == HAL_OK) {
HAL_SPI_Receive(p_setup->hspi, buff, len, p_setup->spi_timeout);
hal_status = HAL_SPI_Receive(p_setup->hspi, buff, len, p_setup->spi_timeout);
}

rf24_end_transaction(p_setup);
Expand All @@ -135,7 +135,7 @@ rf24_platform_status_t rf24_platform_write_register(rf24_platform_t* p_setup, nr
hal_status = HAL_SPI_TransmitReceive(p_setup->hspi, &command, &(status_reg.value), 1, p_setup->spi_timeout);

if (hal_status == HAL_OK) {
HAL_SPI_Transmit(p_setup->hspi, buff, len, p_setup->spi_timeout);
hal_status = HAL_SPI_Transmit(p_setup->hspi, buff, len, p_setup->spi_timeout);
}

rf24_end_transaction(p_setup);
Expand All @@ -159,7 +159,7 @@ rf24_platform_status_t rf24_platform_read_payload(rf24_platform_t* p_setup, uint
hal_status = HAL_SPI_TransmitReceive(p_setup->hspi, &command, &(status_reg.value), 1, p_setup->spi_timeout);

if (hal_status == HAL_OK) {
HAL_SPI_Receive(p_setup->hspi, buff, len, p_setup->spi_timeout);
hal_status = HAL_SPI_Receive(p_setup->hspi, buff, len, p_setup->spi_timeout);
}

rf24_end_transaction(p_setup);
Expand All @@ -180,7 +180,7 @@ rf24_platform_status_t rf24_platform_write_payload(rf24_platform_t* p_setup, uin
hal_status = HAL_SPI_TransmitReceive(p_setup->hspi, &command, &(status_reg.value), 1, p_setup->spi_timeout);

if (hal_status == HAL_OK) {
HAL_SPI_Transmit(p_setup->hspi, buff, len, p_setup->spi_timeout);
hal_status = HAL_SPI_Transmit(p_setup->hspi, buff, len, p_setup->spi_timeout);
}

rf24_end_transaction(p_setup);
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